SUBJECT NAME: VLSI DESIGN. SUBJECT CODE: EC UNIT I CMOS TECHNOLOGY. PART –A (2 MARKS). 1. What are four generations of Integration. EC / EC64 VLSI Design 2 Marks With Answers ECE 6th Semester Regulation | BE Electronics and Communication Engineering. Sixth Semester. 2 MARK QUESTION AND ANSWERS. ECVLSI DESIGN is CMOS technology? Complementary Metal Oxide Semiconductor (CMOS)in which.

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Define Short Channel devices?

It will determine whether the fault coverage exceeds a desired level. Regular event control 2. What is dynamic hazard? The observability of a particular internal circuit node is the degree to which one can observe that node at the outputs of an integrated circuit. Cut off region 2. The load capacitance can be reduced to reduce delay this is achieved by using transistor of smaller and smaller dimension by feature generation technology.

Help Center Find new research papers in: Logic density is less Logic density is higher. What is metastability and list the steps to prevent it?

The completion time is limited by the depth of the carry save array, and by the carry propagation in the adder. These faults most frequently occur due to thin- oxide shorts or metal-to-metal shorts.

High packing density 3. A field programmable gate array FPGA is a programmable logic device that supports implementation of relatively large logic circuits.

Channels gate array Channel less gate array Only the interconnect is 1. No latch up 2. Level-sensitive timing control Types of delay-based timing control: By using sleep transistors to isolate the supply from the block deign achieve significant leakage power savings.


EC VLSI Design Two Marks with Answers – Edition

A carry skip adder consists of a simple ripple carry adder with a special speed up carry chain called a skip chain. What are the disadvantages of dynamic CMOS technology? Define elmore delay model. To store ‘1’, it is charged and to store ‘0’ it is discharged to ‘0’ volt.

Log In Sign Up. What is an antifuse? It must be a single group of characters. By adjusting the body bias i. Different types of oxidation?

A sequencing element with dynamic storage generally maintains its value as charge on a capacitor that will leak away if not refreshed for a long period of time. The major advantages of pipelining are to reduce glitch in complex logic networks and getting qnswers energy due to operand isolation. The threshold voltage, Vt for a MOS transistor can be defined as the voltage applied between the gate and the source of the MOS transistor below which the drain to source current, IDS effectively drops to zero.

What is the structural gate-level modeling? What is known as test data register?


A device connected so as to pull the output voltage to the lower supply voltage usually 0 V is called pull down device. Transistors with channel length less than 3 5 microns are termed as short channel devices.


A device connected so as to pull the output voltage to the upper supply maarks usually VDD is called pull up device. The ansswers of the MOS transistor can be increased to reduce delay this is known as gate sizing, which will be discussed later in more details.


What are gate primitives? What is fault sampling? Static power due to Sub threshold conduction through OFF transistors Tunneling current through gate oxide Leakage through reverse biased diodes Contention current in radioed circuits. What is static power dissipation? Read operation is followed by restoration operation. Output goes momentarily 1 when it should remain at 0 is called static 0 hazard.

Give the steps inASIC design flow.

Give the variety of Integrated Circuits? Draw the full adder diagram using usin CPL. A matrix of programmable interconnect surrounds the basic logic cells. The device that is normally cut-off with zero gate bias. To obtain the functional relationship among the terminal electrical variables of the device that is to be modeled.

What are the general properties of elmore delay model? Answeds number of transistor is getting doubled in every 18 months based on moore’s law Higher speed of operation: Using proper synchronizers two stage or three stageas soon as dezign data is coming from the asynchronous domain.